1. Field of the Invention
The present invention relates to a semiconductor device containing a lateral MOS transistor. More specifically, the present invention relates to technology suitable for use in a high breakdown voltage, low on-resistance, lateral power MOSFET that can be microminiaturized.
2. Description of the Related Art
A high breakdown voltage lateral trench MOSFET disclosed in the Japanese Patent Application Laid-Open No. 8-97411 has, as shown in FIG. 12, a p-type well region 2 formed on a p-type substrate 1, a diffusion layer comprising a source region 9 and a body region 8 formed within the above well region 2 using a double diffusion process with a self alignment technique, and a gate oxide layer 6 and a gate electrode 7 located on top of the structure. Further, a trench 3 is formed by a trench work within a drain drift region 4 to secure the drift length for accomplishing a high breakdown voltage. In the above-described structure, when a gate voltage is applied, electric current flows from a drain region 11 through the drain drift region 4 along the perimeter (A-B-C-D) of the trench 3 to reach a channel region 10. Note that the symbol 5 in FIG. 12 represents an insulation layer formed within the trench 3.
The high breakdown voltage lateral trench MOSFET of the Japanese Patent Application Laid-Open No. 8-97411 has the advantage of achieving a high breakdown voltage by allowing the drift current to flow through the trench region 3 thereby securing a sufficient drift length. However, since the breakdown voltage is determined by the length of the drain drift region 4, it is necessary to make the drift length longer to obtain a higher breakdown voltage. This has presented a disadvantage of a steep rise in on-resistance of a transistor through the increased resistive component of a drain drift region 4. Moreover, when the drain drift region 4 is created by ion implantation and thermal diffusion processes through the trench region 3, this creates an overlapped region between the n-drain drift region 4 and the p-channel region 10. This leads to an increase in the residual crystal defects or crowding of the current flow paths within the diffusion layer which forms a channel, thereby making the device liable to cause a reduction in electron mobility.